1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device which includes an internal voltage generation circuit having a function of generating a high voltage required for data write/erase operations and can reduce an area occupied by the internal voltage generation circuit or suppress an increase in such an area by reducing load applied to an output terminal of the internal voltage generation circuit from which a high voltage is provided.
2. Description of the Related Art
Recently, a nonvolatile semiconductor memory device represented by a flash memory is coming into wide use. The nonvolatile semiconductor memory device has a feature that electric power is not required for holding stored information, and therefore is mainly used in a mobile apparatus, such as a mobile phone or a mobile information processing apparatus, which is severely required to be compact in size and consume low power.
In general, a flash memory often has functions of electrically writing and erasing data and includes an internal voltage generation circuit (hereinafter, referred to as xe2x80x9ccharge pump circuit) having a function of generating a high voltage required for data write/erase operations.
Such a conventional flash memory is described below with reference to FIG. 2. As shown in FIG. 2, the conventional flash memory includes a plurality of memory blocks B1 and B2 (the memory block B2 has a same structure as that of the memory block B1 and is therefore not shown in detail) each including: a memory array M1 including a plurality of memory cells; a plurality of word lines WL and bit lines BL provided so as to cross each other for selecting a memory cell (in this case, the word lines WL and bit lines BL are perpendicular to each other); a row decoder XD for selecting a word line WL according to an externally-input row address signal; and a column decoder YD for selecting a bit line BL according to an externally-input column address signal. Each of the memory blocks B1 and B2 is connected to charge pump circuits PV1 and PV2 so as to provide the voltage required for performing data write/erase operations on the memory arrays M1. A voltage generated by the charge pump circuit PV1 is applied to the row decoder XD in each of the plurality of memory blocks B1 and B2. A voltage generated by the charge pump circuit PV2 is applied to the column decoder YD in each of the plurality of memory blocks B1 and B2. Although a case where the plurality of memory blocks are two memory blocks B1 and B2 is described below, the plurality of memory blocks are not limited to two memory blocks and three or more memory blocks can be used as the plurality of memory blocks.
Next, a voltage to be applied for data write/erase operations is described with reference to a structure of a flash memory shown in FIG. 3. In FIG. 3, reference numerals 1 and 2 denote diffusion regions which respectively form a drain region (D) and a source region (S) of a memory cell. Reference numeral 4 denotes a floating gate (FG) for holding electric charge which is in a state of being fully insulated from electricity by oxide films 3 and 5. Reference numeral 6 denotes a control gate (CG) formed on the oxide film 5. Injection of electric charge into the floating gate 4 (data write) and drawing of electric charge from the floating gate 4 (data erase) are performed by applying a voltage to the control gate 6.
In general, injection and drawing of electric charge (electrons) are performed by means of a tunnel current or activated hot electrons passing through the oxide film 3, and therefore the oxide film 3 is also called a tunnel film. Electric charge injected into the floating gate 4 through the oxide film 3 is semipermanently held in the floating gate 4 if a specific electric field is not applied. Therefore, the flash memory functions as a nonvolatile semiconductor memory device.
Examples of specific values of applied voltage are described below. In the case of a data write operation by means of the injection of hot electrons, for example, a high voltage of 12V is applied to the control gate 6, a high voltage of 6V is applied to the drain region 1, and zero voltage is applied to the source region 2. This allows a channel to be formed between the source and drain regions 2 and 1, so that a large current flows through the channel (electron migration from the source region 2 to the drain region 1). After the migration from the source region 2 to the drain region 1, each electron has a large energy due to the high voltage applied to the drain region 1. When an electron has higher energy than that of an energy barrier of an insulation film (oxide film 3), the electron can migrate to the floating gate 4. According to this mechanism, the injection of the electrons into the floating gate 4 brings a memory cell into a data write state.
On the other hand, in the case of a negative voltage erase method which is one of the methods for drawing electrons stored in a floating gate into a source of a memory cell, for example, a voltage of xe2x88x9210V is applied to the control gate 6, zero voltage is applied to the source region 2, and the drain region 1 is brought into a floating (high impedance) state. This allows electrons to migrate from the floating gate 4 to the source region 2 due to a tunnel effect, thereby erasing data in the memory cell.
As described above, in order to perform data write/erase operations on a flash memory cell, either of positive or negative voltages, which is higher than a normal power supply voltage, is required. Such a high voltage or a negative voltage is applied to a drain of the flash memory cell via a bit line connected thereto and a control gate of the flash memory cell via a word line connected thereto.
When performing a data write operation, the charge pump circuit PV1 generates, for example, a voltage of 12V which is applied to a predetermined word line via a row decoder XD in a selected memory block and the charge pump PV2 generates, for example, a voltage of 6V which is applied to a predetermined bit line via a column decoder YD in the selected memory block. As a result of this, data is written in a memory cell in which the predetermined word and bit lines cross each other. In an unselected memory block, no voltage is applied to any one of word and bit lines by the charge pump circuits PV1 and PV2.
However, in the conventional structure described above, the charge pump circuits PV1 and PV2 are respectively connected to the row decoders XD and the column decoders YD of all the memory blocks, and therefore a large load is applied to each of the charge pump circuits PV1 and PV2.
Accordingly, when a current application ability of a charge pump circuit is weak, a voltage applied by that charge pump circuit to a memory array is reduced, so that a data write property of the charge pump circuit with respect to the memory array is deteriorated, thereby causing problems, e.g., a period of time required for a data write operation is lengthened. Further, similar problems are caused with respect to a data erase operation on the memory array.
Therefore, in the conventional nonvolatile semiconductor memory device, as memory capacity is increased, a size of a charge pump circuit is also required to be increased, thereby further increasing an area of a semiconductor chip.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a plurality of memory blocks each including a memory array including a plurality of memory cells, a plurality of word lines and bit lines provided so as to cross each other for selecting the memory cell, a row decoder for selecting the word line according to an externally-input row address signal, a column decoder for selecting the bit line according to an externally-input column address signal; and at least one internal voltage generation circuit for applying a voltage required for performing data write/erase operations on the memory array, a plurality of first switch circuits are provided such that each first switch circuit is provided between the at least one internal voltage generation circuit and the row decoder or the column decoder, and a switch selection circuit is provided for selectively operating the plurality of first switch circuits.
In one embodiment of the invention, the at least one internal voltage generation circuit includes a charge pump circuit and has a function of generating a voltage which is higher than a positive or negative power supply voltage.
In another embodiment of the invention, each first switch circuit has a function of electrically connecting and disconnecting the at least one internal voltage generation circuit to the memory block so as to selectively apply an output voltage provided by the internal voltage generation circuit to the memory block.
In still another embodiment of the invention, the switch selection circuit has a function of outputting a signal for selecting at least one of the plurality of first switch circuits according to an externally-input address signal.
In still another embodiment of the invention, each first switch circuit is formed of a P-channel-type MOS transistor.
In still another embodiment of the invention, a plurality of second switch circuits are provided such that one of a source and a drain of each second switch circuit is connected to an output terminal of a corresponding one of the plurality of first switch circuits provided between the at least one internal voltage generation circuit and the row decoder or the column decoder and the other one of the source and the drain thereof is grounded, and each second switch circuit has a function of grounding a connection point between the row or column decoder and the corresponding one of plurality of first switch circuits when the corresponding one of plurality of first switch circuits is electrically disconnected.
In still another embodiment of the invention, each second switch circuit is formed of an N-channel-type MOS transistor.
Functions of the present invention are described below.
In the present invention, a first switch circuit provided between an internal voltage generation circuit (a charge pump circuit) and a row or column decoder is selectively operated using a switch selection circuit. By connecting the charge pump circuit only to a memory block selected from a plurality of memory blocks so as to apply an output voltage from the charge pump circuit to the selected memory block, it is possible to reduce the load applied to the charge pump circuit.
In order to conduct a high voltage generated by the charge pump circuit without reducing potential of the high voltage, it is preferable to use a P-channel-type MOS transistor as the first switch circuit.
Further, by providing a plurality of second switch circuits such that one of a source and a drain of each second switch circuit is connected to an output terminal of the first switch circuit and the other one of the source and the drain thereof is grounded and grounding the row or column decoder when the first switch circuit is electrically disconnected, it is possible to reduce the load applied to the charge pump circuit connected to the row or column decoder.
Since an N-channel-type MOS transistor is superior in conductive properties to a P-channel-type MOS transistor, it is preferable to use the N-channel-type MOS transistor as the second switch circuit which is a transistor having ground potential as source potential.
Thus, the invention described herein makes possible the advantages of providing a nonvolatile semiconductor memory device which can reduce the load applied to an internal voltage generation circuit without deteriorating data write/erase properties, so that a size of the internal voltage generation circuit is kept minimum, thereby preventing an increase in area of a semiconductor chip.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.